1. Technical Field
The present invention relates generally to semiconductor design technology, and more particularly, to a CAS latency setting circuit for performing a test and a semiconductor memory apparatus including the same.
2. Related Art
Typically, a semiconductor memory apparatus is designed using a synchronous clock in order to improve data transmission speed. For example, when an external command such as a read command is received in synchronization with an external clock, a synchronous DRAM (SDRAM) may output data from a memory cell in synchronization with a clock signal after a predetermined clock cycle from the read command. The time delay from when the clock signal is synchronized with the external command to when the clock signal is synchronized with the output data is referred to as column address strobe (CAS) latency.
In general, CAS latency is set by information bits stored in a mode register set (MRS) inside a semiconductor memory apparatus. For example, referring to FIG. 1, CAS latency may be set according to predetermined address information when a MRS command is inputted. That is, the CAS latency may be arbitrarily set according to the initial setting of the MRS. Accordingly, a synchronous semiconductor memory apparatus outputs read data externally after a time delay corresponding to the CAS latency from a clock signal synchronized with an external read command.
Typically, a system using the synchronous semiconductor memory apparatus sets the CAS latency of the semiconductor memory apparatus to a specified value without modifying the CAS latency thereafter. As illustrated in FIG. 2, the synchronous semiconductor memory apparatus 100A sets a fixed CAS latency during the initial setting, thereby solely controlling output timings of data after a read command is applied.
Referring to FIG. 2, the semiconductor memory apparatus 110A includes a CAS latency setting unit 10, an output enable signal generation unit 40, and an output driver 50.
The CAS latency setting unit 10 is configured to set a CAS latency value CL according to specific address information such as address information A<2,4,5> as illustrated in FIG. 2, when an MRS command is applied. The CAS latency setting unit 10 may include an MRS configured to perform the initial settings of the semiconductor memory apparatus.
The output enable signal generation unit 40 is configured to receive the CAS latency value CL and generate an output enable signal OEFLAG by shifting a read signal pulse RD applied from an external source. The output enable signal OEFLAG is a signal which is activated to output read data externally. When the read signal pulse RD is shifted, a delay amount based on the entire data output path of the semiconductor memory apparatus may be considered to generate the output enable signal at a specified time.
The output driver 50 is configured to output the read data DATA as output data DOUT externally at a time when the output enable signal OEFLAG is activated.
When the CAS latency value CL is set at the initial stage, the conventional synchronous memory apparatus has a data output timing depending on the set CAS latency value CL when the read signal pulse RD is applied. Therefore, data processing may be performed quickly and precisely between the semiconductor memory apparatus and a processor inside the system.
For this reason, the synchronous semiconductor memory apparatus has a fixed CAS latency according to the initial settings. During a production design process, however, the synchronous semiconductor memory apparatus is designed to implement various CAS latency values to operate properly under different system environments.
Therefore, after a synchronous semiconductor memory apparatus is fabricated, testing is conducted to determine whether proper operation under various CAS latency values is achieved. However, it is very inefficient to set various CAS latency values by changing settings of a mode register set during each test. Accordingly, there is a demand for a semiconductor memory apparatus capable of operating at a fixed CAS latency value in a normal mode, and efficiently testing various CAS latency values in a test mode.